Layout
How to build a fair PCB autorouter benchmark
PCBBench editorial · Published October 14, 2026 · Editorial policy
A fair autorouter benchmark gives every router the same board state, allowed edits, stackup and design rules. It distinguishes an unfinished board from a fully connected, rule-compliant result before comparing routing efficiency.
Choose a varied board set
Include different package pitches, connector arrangements and congestion patterns. Keep a record of unrouted connections and any pre-existing violations in each input. An input defect should not unexpectedly become an obligation for one entrant while another router is judged only on newly created tracks.
Keep budgets and retry policies visible
Declare compute limits, thread counts and whether failed attempts can restart. Save every attempt, including crashes. If a tool chooses the best of several outputs, give every entrant the same opportunity and distinguish that policy from first-attempt performance.
Make the board checker independent
Refill zones and run the target EDA checks on the submitted artifact. Compare intended connectivity with the input netlist, not only the router's internal success flag. Freeze rule files outside the editable output where the evaluation environment permits it.
Practical checklist
- Version every input board.
- Publish the allowed edit policy.
- Set equal retry and compute budgets.
- Record crashes and incomplete routes.
- Compare quality only after validity gates.
A concrete example
Run three routers on a dense connector board.
- Evidence to accept
- The report includes clean completion, runtime, vias and trace length for each attempt.
- Evidence that is insufficient
- The best seed is reported for one router while the others receive one attempt.
Common questions
Can synthetic boards be useful?
Yes, especially for controlled congestion tests. Real boards add placement and electrical context that synthetic instances may omit.
Should timeout count as a bad board?
Report timeout as its own outcome and state how it affects the aggregate. Do not silently remove it.
Primary references and further reading
Use the matching device documentation and project configuration when applying this checklist. These references explain the underlying tools and evaluation approaches.
How this fits PCBBench
The AI PCB placement and routing benchmark describes the proposed inputs, outputs and checks for this capability. The pilot snapshot contains partial measured attempts; it is not a finished ranking.
Related reading
- How to evaluate AI PCB placement and routingAssess AI PCB layouts with connectivity gates, fixed manufacturing rules and electrical placement constraints.
- KiCad DRC checklist before PCB fabricationA practical DRC review covering rule profiles, zone refill, unconnected items, exclusions and schematic parity.
- Autorouting vs AI PCB designUnderstand what a PCB autorouter solves and what remains in component selection, schematics, placement and release.