Proposed Season 1 protocol
AI PCB placement and routing benchmark
Can the system finish a fixed board problem while preserving connectivity, rules and electrical intent?
What the task receives
A netlist or board state, outline, stackup, fixed rule profile and permitted placement edits.
What counts as evidence
A native PCB with complete intended connectivity and clean required checks before routing quality is compared.
Lock input invariants and compare the submitted board against them. Refill zones and independently run the target checks. Report completion, rule compliance, runtime, vias and trace length separately, with circuit-specific geometry checks where the task defines them.
Failure cases the evaluation should catch
- Deleting a difficult connection to report routing completion.
- Changing pad identities, board rules or the outline without permission.
- Reducing wirelength while creating a poor return path.
Illustrative task brief
Place and route on the given 40×30 mm outline, 2 layers, JLCPCB 6/6 mil rules. Crystal within 5 mm of the MCU, decoupling within 2 mm of each supply pin, USB pair at 90 Ω.
This example describes the intended task format. It is not a published model result, and the exact task acceptance contract must accompany its frozen inputs.
Metrics to report
- Clean pass
- Routed %
- Physics rule checks
- Vias and wirelength vs reference
Limits of this evidence
Geometric checks do not replace full electrical, thermal or mechanical validation.
Read the proposed methodology and dated pilot snapshot before interpreting any result. Partial pilot averages cover different task mixes and do not establish a model ordering.