Layout
KiCad DRC checklist before PCB fabrication
PCBBench editorial · Published October 14, 2026 · Editorial policy
Run DRC against the manufacturing and electrical rules intended for the actual board. A clean report is meaningful only when the checked artifact, rule deck, exclusions and connectivity expectations are known.
Start from the correct fabrication profile
Record the layer stack and the board manufacturer's capabilities used by the project. Check net classes and custom rules as well as global defaults. Do not substitute a convenient default profile merely because it produces fewer errors.
Check the final board state
Refill copper zones before the final check and verify that schematic and board connectivity agree. Review remaining unconnected items explicitly. Exporting Gerbers from an older revision after checking a newer board breaks the chain of evidence.
Resolve exceptions one by one
Keep a reason for each exclusion and separate inherited input findings from changes introduced by a tool. Mechanical fit, thermal behavior and signal integrity may need checks beyond the configured DRC rules, so preserve those as separate release criteria.
Practical checklist
- Verify stackup and fabrication rules.
- Refill zones.
- Check schematic-to-board parity.
- Resolve unconnected items and exclusions.
- Export only from the checked revision.
A concrete example
Release a two-layer board for manufacturing.
- Evidence to accept
- The report and exports come from the same revision with the chosen fabrication profile.
- Evidence that is insufficient
- The board passes after the clearance rule is relaxed without approval or documentation.
Common questions
Does zero DRC mean fabrication-ready?
It is one release gate. Assembly data, footprints, mechanical details and the export package still need validation.
Can old violations be ignored in a routing test?
Only with an explicit baseline policy. Preserve the baseline report and reject unexplained regressions.
Primary references and further reading
Use the matching device documentation and project configuration when applying this checklist. These references explain the underlying tools and evaluation approaches.
How this fits PCBBench
The AI PCB placement and routing benchmark describes the proposed inputs, outputs and checks for this capability. The pilot snapshot contains partial measured attempts; it is not a finished ranking.
Related reading
- How to evaluate AI PCB placement and routingAssess AI PCB layouts with connectivity gates, fixed manufacturing rules and electrical placement constraints.
- How to build a fair PCB autorouter benchmarkCompare PCB autorouters with fixed inputs, completion checks, DRC gates and explicit routing-quality metrics.
- Autorouting vs AI PCB designUnderstand what a PCB autorouter solves and what remains in component selection, schematics, placement and release.