How to evaluate AI PCB placement and routing

Lock everything the router is not allowed to change

Preserve the outline, pad identities, footprints, layer stack and rule configuration. Explicitly state whether component movement, pin swapping or changes to net classes are allowed. Save hashes or structured diffs so the checker can detect a solution that silently changes the problem.

Use placement constraints that describe the circuit

Define relationships such as a local bypass loop, an accessible connector or a protected keepout. Avoid a universal distance threshold copied onto every component. The relevant current loop and return path depend on the exact device and operating conditions.

Compare quality among valid boards

After hard gates pass, inspect trace length, via count, congestion and relevant electrical geometry. Report the metrics separately rather than hiding all tradeoffs in one score. A denser board or a different stackup can make raw totals misleading across tasks.

Practical checklist

1. Freeze board and rule inputs.
2. Check pad-to-net assignments.
3. Require complete intended connectivity.
4. Rerun DRC after zone refill.
5. Review current loops and return paths.

A concrete example

Route two candidate layouts from one netlist and outline.

Evidence to accept

Both preserve pad identity and satisfy the same rule deck before quality is compared.

Evidence that is insufficient

One candidate deletes a difficult pad or changes clearance to achieve a cleaner report.

Common questions

Primary references and further reading

Use the matching device documentation and project configuration when applying this checklist. These references explain the underlying tools and evaluation approaches.

• KiCad PCB editor documentation
• PCBWorld: engine-grounded PCB design automation