Schematics
KiCad ERC checklist for AI-generated schematics
PCBBench editorial · Published October 14, 2026 · Editorial policy
Use KiCad ERC as a repeatable connectivity and pin-type check, then review the requirements it does not encode. An empty ERC report can coexist with a wrong resistor value, an unsuitable regulator or an incorrect connector assignment.
Check the setup before the findings
Save the KiCad version, project configuration and severity settings. Inspect exclusions and no-connect markers. A generated answer should not earn a clean result by downgrading a failure or adding markers that merely silence an unresolved connection.
Trace findings to design intent
Follow a reported connection through labels and hierarchy rather than judging isolated symbols. Decide whether an undriven power net is a modeling issue or a real missing supply connection. Document justified exceptions so the same rule is applied on the next run.
Review what ERC cannot establish
Verify exact part pinouts, electrical ratings and expected operating states. Check that values and tolerances support the brief. Keep these requirements in a separate checklist so an ERC pass is not accidentally presented as complete circuit validation.
Practical checklist
- Save the rule configuration.
- Review excluded findings.
- Verify power sources and hierarchy.
- Inspect no-connect markers.
- Check ratings and values separately.
A concrete example
Review a generated power rail that uses a custom regulator symbol.
- Evidence to accept
- Pin mapping and supply intent are correct, and exceptions have a documented reason.
- Evidence that is insufficient
- Power flags are added everywhere without checking whether the supplies exist.
Common questions
Are all ERC warnings real defects?
No. Symbol models and project conventions can produce justified exceptions. Review and document them rather than ignoring all warnings.
Can I use ERC in automation?
KiCad provides command-line checks. Record the command, version, configuration and report with the evaluated schematic.
Primary references and further reading
Use the matching device documentation and project configuration when applying this checklist. These references explain the underlying tools and evaluation approaches.
How this fits PCBBench
The AI schematic generation benchmark describes the proposed inputs, outputs and checks for this capability. The pilot snapshot contains partial measured attempts; it is not a finished ranking.
Related reading
- How to test AI schematic generationTest an AI-generated schematic for electrical intent, real components, valid connectivity and reproducible verification.
- Netlist equivalence for AI schematic validationValidate pin-level circuit intent while allowing equivalent drawing layouts and legitimate alternative implementations.
- Using SPICE to validate AI-generated circuitsUse simulation as a requirements test with explicit models, operating points, tolerances and known limits.
- SPICE vs ERC: simulation and schematic checksCompare circuit simulation with electrical-rule checking and choose evidence for each requirement.