Verification
SPICE vs ERC: simulation and schematic checks
PCBBench editorial · Published October 14, 2026 · Editorial policy
ERC tests configured connection rules; SPICE evaluates a modeled circuit under specified stimuli. They complement each other because structural correctness and modeled electrical behavior are different questions.
Use ERC for structural diagnostics
ERC can identify suspect pin interactions and connections based on the symbol and project rules. It does not compute whether an amplifier has the requested gain or a power stage behaves correctly under a load transient.
Use simulation for measurable behavior
Define stimuli, models and acceptance ranges before running SPICE. Inspect operating points and relevant corners. Simulation can still produce a persuasive result for the wrong physical device if the model mapping or assumptions are incorrect.
Connect both to the actual design
Ensure the simulated netlist corresponds to the intended schematic. Preserve model versions and testbench files. Review non-modeled requirements, part ratings and assembly mapping rather than treating one successful analysis as a complete release decision.
Practical checklist
- Run structural checks.
- Verify model pin assignments.
- Define numerical observations.
- Test relevant operating conditions.
- Review unmodeled requirements.
A concrete example
Validate a generated sensor amplifier.
- Evidence to accept
- ERC checks structure and simulation checks required transfer behavior under stated conditions.
- Evidence that is insufficient
- The simulator converges, so the board is claimed correct without checking the model or footprint.
Common questions
Can SPICE catch a mistake ERC misses?
Yes, when the mistake affects modeled behavior covered by the test.
Can ERC catch something a simulation misses?
Yes. The simulation may omit parts of the design or use simplified component models.
Primary references and further reading
Use the matching device documentation and project configuration when applying this checklist. These references explain the underlying tools and evaluation approaches.
How this fits PCBBench
The AI schematic generation benchmark describes the proposed inputs, outputs and checks for this capability. The pilot snapshot contains partial measured attempts; it is not a finished ranking.
Related reading
- How to test AI schematic generationTest an AI-generated schematic for electrical intent, real components, valid connectivity and reproducible verification.
- KiCad ERC checklist for AI-generated schematicsReview electrical-rule results without hiding connection mistakes, changing severity settings or overlooking wrong component values.
- Netlist equivalence for AI schematic validationValidate pin-level circuit intent while allowing equivalent drawing layouts and legitimate alternative implementations.
- Using SPICE to validate AI-generated circuitsUse simulation as a requirements test with explicit models, operating points, tolerances and known limits.